About us

We are Yamasaki lab at Keio University specializing in the design and development of advanced computing hardware and software architectures. Our interdisciplinary approach integrates both hardware and software innovations to solve complex challenges in computing systems.

Our core research areas include (but not limited to):

• VLSI design & hardware architecture

  Researching custom CPU and GPU architectures, covering the full design stack from RTL-level microarchitecture design, instruction set customization, and pipeline optimization to system-level integration with memory subsystems and interconnects. Our work targets both high performance and low power consumption, making it suitable for real-time embedded systems, edge computing, and application-specific accelerators.

• Real-time systems & scheduling algorithms

  Developing advanced real-time scheduling techniques to guarantee strict timing constraints for time-critical systems. This includes support for periodic, sporadic, and aperiodic tasks, with considerations for deadlines, worst-case execution time (WCET), and system utilization. In addition to software algorithms, we also design hardware support mechanisms to enable predictable, low-latency task management in custom SoCs and real-time processors. Our research spans mixed-criticality systems, multi-thread/multi-core scheduling, and energy-efficient execution for domains like automotive, industrial automation, and space systems.

• Embedded hypervisors

  Creating secure and efficient virtualization solutions tailored for real-time and multi-OS embedded environments. This includes the design and implementation of lightweight hypervisors with support for inter-VM isolation, low-latency context switching, and real-time task scheduling across virtual machines. Our virtualization frameworks are optimized to run multiple operating systems on a single hardware platform, enabling safe partitioning, fault containment, and resource sharing. We also explore hardware-assisted virtualization, interrupt routing, and memory protection mechanisms to minimize overhead and ensure predictable performance in safety-critical systems.

• Communication systems

  Exploring advanced communication technologies, including optical fiber networks and codec architectures, to enable high-speed, low-latency, and energy-efficient data transfer. Our research covers the design of custom transmission line codes, error detection mechanisms, and lightweight framing techniques for low Bit Error Rate (BER) environments such as error-free plastic optical fiber (POF). In addition, we develop real-time communication protocols and dedicated hardware modules that ensure deterministic latency, jitter control, and timing predictability, making them ideal for embedded real-time systems, industrial automation, and autonomous systems.

Our lab combines theoretical foundations with practical implementation to support both academic discovery and industrial innovation. We actively collaborate with international partners and welcome students from around the world who are passionate about building the next generation of computing systems.

Why join our lab?

We offer a hands-on, end-to-end research experience that spans hardware, software, and everything in between.

From RTL to real silicon

We take chip design beyond the classroom. Students in our hardware group gain rare, full-cycle experience in:

• Designing custom SoCs at the RTL (Register Transfer Level)

• Simulating, synthesizing, and implementing these designs using industry-standard tools (Synopsys, Cadence, Siemens, etc.)

• Completing the full GDS layout, ready for fabrication by foundries (TSMC, Sony, etc.)

• Developing System-in-Package (SiP) modules that integrate the chips into deployable systems

This is a unique opportunity to see your own digital logic come to life in physical form — a hands-on journey from HDL code to silicon hardware.

Real-time OS from scratch

In parallel with hardware development, we build custom real-time operating systems specifically tailored to our own SoCs. This allows students to:

• Write the boot sequence to initialize custom hardware from power-on

• Design and implement a real-time scheduler to manage concurrent tasks with timing guarantees

• Handle interrupts, context switching, and memory management from scratch

• Extend the OS with a lightweight, embedded hypervisor, enabling secure multi-OS environments or virtualized systems

• Develop a custom compiler to utilize custom instructions (GCC-based, LLVM-based)

This full-stack systems engineering experience is ideal for those passionate about OS internals, embedded systems, and real-time computing.

Research Environment

Evaluation boards to test the fabricated custom SoCs.

Picture of one of our lab's FPGA boards.

We believe that a great learning environment fosters great innovation. That’s why our lab is equipped with:

• Multiple high-performance server machines for large-scale simulation, synthesis, software compilation, and verification

• An extensive collection of FPGA development boards (VCU128, VCU129, VPK120 x 2, VPK180), used to test and validate custom hardware designs

• Weekly interactive lectures led by our professor, covering topics that students request — ranging from low-level transistor behavior to operating system design and scheduling theory

You’ll be surrounded by advanced resources and supportive mentorship — all of which help you grow both as a researcher and as an engineer.

Research topics

Our lab conducts cutting-edge research across both hardware and software domains. We focus on building real-time, efficient, and secure systems from the operating system layer down to silicon. Below are some examples of our research topics:

Hardware group

Multithreaded RISC-V Processor

Block diagram of the Multithreaded RISC-V Processor.

Examples of dynamic thread control instructions.

This research presents the design and implementation of a multithreaded RISC-V processor tailored for real-time systems. Addressing the lack of built-in multithreading support in the standard RISC-V ISA, we introduce a novel architecture capable of dynamic thread creation, deletion, and priority-based scheduling across eight logical cores. A custom instruction set enables dynamic thread control, while a context cache allows rapid context switching in just four cycles, supporting execution of more threads than cores. Evaluation shows a 5.5x IPC improvement over single-threaded execution, making this work highly relevant for embedded and time-sensitive applications.

Non-volatile processor

Block diagram of the non-volatile processor Soc/SiP.

Picture of the non-volatile processor SiP.

This research presents the design and implementation of a fault-tolerant real-time system-on-chip (SoC) and system-in-package (SiP) capable of continuous operation even under unstable power conditions — critical for safety-focused embedded systems like automobiles, spacecraft, and sensor networks. The custom SoC integrates a non-stop microprocessor, MRAM (non-volatile memory), SRAM, and I/O peripherals, allowing it to retain system state on power interruptions. To extend functionality, a co-designed SiP combines the SoC with an FPGA, USB power delivery, DC/DC converters, and additional components on a compact board.

Real-time processor: Responsive Multithreaded Processor

Block diagram of the Responsive Multithreaded Processor SoC.

Picture of the Responsive Multithreaded Processor SiP.

This research focuses on the development of a simultaneous multithreading (SMT) processor specifically designed for real-time embedded systems. The processor features an 8-way superscalar, out-of-order execution architecture, capable of executing up to 8 threads simultaneously for high throughput and responsiveness. To meet the stringent demands of real-time workloads, the processor incorporates a range of hardware-based real-time support mechanisms, including dynamic thread control, context cache, interruption wake-up, and IPC control mechanism. This architecture enables precise scheduling, low-latency execution, and resource isolation, making it ideal for distributed and safety-critical systems.

RISC-V based GPU

Block diagram of the compute unit of the proposed GPU.

Block diagram of the SIMD unit of the compute unit.

This research explores the design of a RISC-V-based GPGPU architecture that enhances data processing efficiency by integrating a SIMD (Single Instruction Multiple Data) execution unit into its compute core. The architecture leverages the open and flexible RISC-V ISA, making it well-suited for embedded systems. To further boost performance, the system supports low-precision data types, enabling faster computation with an acceptable trade-off in accuracy — ideal for workloads such as machine learning and video processing.

Codec for ultra-low error rate plastic optical fiber (POF)

Wave model of PAM4 (Pulse Amplitude Modulation 4), which is used in POF.

Proposed codec structure for POF.

This research focuses on developing a lightweight transmission line code tailored for error-free Plastic Optical Fiber (POF), a promising technology for high-speed, low-latency, and low-power communication in data centers. By leveraging POF’s low error rate, the design eliminates the need for traditional Forward Error Correction (FEC) and Frame Check Sequence (FCS) processing, significantly reducing latency and hardware complexity.

Software group

Mixed criticality systems (MCS) scheduling

Proposed task level mode model.

Example of MCS with proposed model applied.

This research proposes a new Mixed-Criticality (MC) task model for embedded real-time systems, targeting tasks whose execution time varies based on input data. Unlike traditional models that use fixed worst-case execution time (WCET) estimates, the proposed model represents WCET as a function of algorithmic complexity, enabling more accurate scheduling of data-dependent tasks. Additionally, a novel online task control method is introduced to reduce the number of discarded non-critical tasks when critical tasks overrun. By selectively dropping only the necessary non-critical tasks based on required resources, the system achieves higher execution efficiency and better overall performance.

Embedded real-time hypervisor OS: iRMTvisor

Example of iRMTvisor applying 'IPC stealing' to logical cores in a guest virtual machine.

This research introduces iRMTvisor, a lightweight hypervisor designed for the Responsive Multithreaded Processor (RMTP) — a simultaneous multithreading (SMT) processor tailored for distributed real-time systems. iRMTvisor enables instruction per clock (IPC) control, allowing precise real-time thread scheduling within virtual machines without cross-VM interference. By leveraging RMTP’s unique execution control and a context cache, the system can handle more threads than available logical cores.

Recommended backgrounds

We welcome students from all over the world who are motivated to work on real-time systems, embedded computing, computer architecture, and so on. While we provide mentorship and learning opportunities, the following backgrounds will help you engage more deeply with our research.

Hardware group

• Basic CPU architecture

  Understanding of core processor design concepts such as in-order execution, pipelining, superscalar architectures, and out-of-order execution.

• Instruction Set Architecture (ISA)

  Familiarity with common ISAs such as MIPS or RISC-V, including knowledge of instruction formats, control flow, and data path elements.

• Hardware Description Language (HDL)

  Ability to read and write HDL such as VerilogHDL, including hierarchical modules, testbenches, and synthesizable design practices.

• Simulation tools

  Experience using tools like XMVerilog, Synopsys VCS, or equivalent simulators to test and debug RTL designs.

• Waveform viewer tools

  Familiarity with waveform analysis tools such as SimVision or GTKWave to observe signal behavior, timing, and logic correctness.

Software group

• Operating systems

  Understanding of OS fundamentals such as the boot sequence, memory management, interrupt handling, and task scheduling is essential for working with real-time and embedded OS environments.

• Assembler & Instruction Set Architecture (ISA)

  Ability to read and write assembly code for architectures like MIPS or RISC-V, especially when working close to the hardware or during early system bring-up.

• C programming

  Proficiency in C is critical, especially for writing low-level system software, including startup code, device drivers, and OS kernels.

• Compiler knowledge

  Familiarity with GCC or LLVM toolchains, including common compiler and linker options, cross-compilation, and how source code is transformed into executables.

• Large scale compilation

  Understanding how to read and write Makefiles to build and manage multi-file software projects efficiently.

Common for all students

• Familiarity with Linux

  Understanding of basic Linux commands, file system structure, and the ability to write and use shell scripts.

• Curiosity and initiative

  A proactive attitude, eagerness to learn, and the ability to explore unfamiliar topics independently.

• Communication and collaboration

  Willingness to share ideas, ask questions, and contribute to a collaborative, multilingual research environment.

• Documentation and technical writing

  Ability to clearly explain your work in code comments, reports, and presentations is highly valued in our lab.

Contact

For inquiries, applications, or questions, please contact:
yamasaki{_at_}ny.ics.keio.ac.jp
(replace {_at_} with @)

Please include the following in your email if you're inquiring about research opportunities:

• Your name and academic background

• A brief self-introduction and research interests

• Your CV and academic transcript (if available)

We welcome motivated students from all over the world and look forward to exploring the future of advanced computer systems together!