Yamasaki Lab

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Sorry, this entry is only available in JAPANESE/日本語.

November 19 (Wed) – 21 (Fri), 2025 | Pacifico Yokohama

Yamasaki Laboratory will exhibit its project at EdgeTech+ 2025, a comprehensive exhibition focused on accelerating the social implementation of innovation through edge technologies. The event will be held at Pacifico Yokohama from November 19 (Wednesday) to 21 (Friday), 2025.

EdgeTech+ is a platform that adds new value to edge technologies, driven by customer-centric innovation. It is a comprehensive exhibition where visitors can explore the latest technologies essential for driving business transformation.

We invite you to visit and explore our booth at the event.

For more information about EdgeTech+ 2025, please visit [this page].

For details about Yamasaki Laboratory’s booth, please click [here].

We are pleased to announce that an article about our “Nonstop Processor” has been published by The Denpa Shimbun.

The article highlights the unique features of the Nonstop Processor developed by our laboratory, as well as its future prospects.

Link to the article: https://dempa-digital.com/article/694131

Yahoo! News coverage: https://news.yahoo.co.jp/articles/a75f17c8a2d8a08dae99a0ef754c8784202728b8

We exhibited at University Fair 2025- Innovation Japan, held at Tokyo Big Sight on August 21(Thu) – August 22(Fri).

Our exhibit featured the theme: “Non-stop Processor/Processor for Distributed Real-Time Processing.”

For more details about University Fair 2025, please refer to [this page]

Shota Nakabeppu received the Young Researcher Award from the System Architecture (ARC) Workshop.

• Shota Nakabefu, Nobuyuki Yamazaki, “Non-stop Processor Using MTJ-based Non-volatile Devices”, Presented at the ARC Workshop, March 2024

Wada, Muto and Sanuki presented at 252th System Architecture Conference, the 208th System and LSI Design Technology Conference, and the 68th Embedded Systems Joint Research Presentation (ETNET2025).

URL: https://www.ipsj.or.jp/kenkyukai/event/arc252sldm208emb68.html

March 18 (Thu), 09:00-10:20
[CPSY+DC] High Reliability
(2) Kohei Wada and Nobuyuki Yamasaki, “Design of a Lightweight Codec for Error-Free POF”

March 18 (Fri), 10:35-12:35
[CPSY+ARC] Processor Architecture
(17) Keita Muto and Nobuyuki Yamasaki, “Design of a Compute Unit for GPGPU Using RISC-V ISA”
(19) Haruka Sanuki, Nobuyuki Yamasaki, “Design and Implementation of iRMTvisor: A Hypervisor for RMT Processors with IPC Control”

Sato and Yamazawa presented at The Twelfth International Symposium on Computing and Networking (CANDAR2024).

URL: https://is-candar.org/

November 27th (Wed) 13:30-15:10
“A Learning-based Control Scheme for Prioritized SMT Processor”, Kaname Sato and Nobuyuki Yamasaki

November 28th (Thu) 10:45-12:25
“Context Cache for Multicore RISC-V Processor”, Akira Yamazawa, Tsutomu Itou, Kazutoshi Suito and Nobuyuki Yamasaki

November 20 (Wed) – 22 (Fri), 2024 | Pacifico Yokohama

Yamasaki Laboratory will exhibit its project at EdgeTech+ 2024, a comprehensive exhibition focused on accelerating the social implementation of innovation through edge technologies. The event will be held at Pacifico Yokohama from November 20 (Wednesday) to 22 (Friday), 2024.

EdgeTech+ is a platform that adds new value to edge technologies, driven by customer-centric innovation. It is a comprehensive exhibition where visitors can explore the latest technologies essential for driving business transformation.

We invite you to visit and explore our booth at the event.

For more information about EdgeTech+ 2024, please visit [this page].

For details about Yamasaki Laboratory’s booth, please click [here].