Yamasaki Lab

We are pleased to announce that in May 2025, the error-correcting line code 4b/10b, developed by the Yamasaki Laboratory, has been officially published as an international standard IEC 63455:2025.

4b/10b is a table-based line code that converts 4-bit data into 10-bit symbols.
This code achieves 1-bit error correction and 2-bit error detection solely through table lookup, while also providing DC balance and clock embedding performance superior to 8b/10b.
This enables low-latency, stable communication even in noisy environments, making it a suitable code for real-time communication.

For more details, please refer to the following URL:

https://webstore.iec.ch/en/publication/73887

We will exhibit at KEIO TECHNO-MALL 2025, which will be held on Friday, December 12, 2025. At our booth, we will present a live demonstration of our non-stop processor and introduce our latest research results. Please feel free to stop by if you are interested.

Date: December 12, 2025 (Fri)

Venue: Tokyo International Forum, Basement Level 2 (Hall E2)

Booth Number: 61

Exhibition Content: Live demonstration of the non-stop processor Introduction of our research on processors for distributed real-time processing

For more details about KEIO TECHNO-MALL 2025, please visit this page.

Sanuki presented at The Thirteenth International Symposium on Computing and Networking (CANDAR2025)
Yanagi presented at 16th International Workshop on Advances in Networking and Computing (WANC2025) (CANDARW2025)
Kogure presented a poster at the same conference.

CANDAR URL: https://is-candar.org/
WANC URL: https://is-candar.org/wanc25

November 26th (Wed) 13:10-14:50
“iRMTvisor: A Real-Time Hypervisor with IPC Control Scheme”, Haruka Sanuki and Nobuyuki Yamasaki

November 27th (Wed) 13:10-14:50
“Pseudo-SMT Processor with Context Cache”, Moyo Yanagi and Nobuyuki Yamasaki

November 28th (Wed) 12:00-13:00
“Exploring Shared Reservation Stations for Embedded Processors”, Kazuki Kogure and Nobuyuki Yamasaki

Wada presented at The 33rd International Conference on Plastic Optical Fibers (POF2025)

URL: https://pof2025.org/

October 30th (The) 14:40-15:00
“Design of Light Codec for Error-free POF”, Kohei Wada and Nobuyuki Yamasaki

November 19 (Wed) – 21 (Fri), 2025 | Pacifico Yokohama

Yamasaki Laboratory will exhibit its project at EdgeTech+ 2025, a comprehensive exhibition focused on accelerating the social implementation of innovation through edge technologies. The event will be held at Pacifico Yokohama from November 19 (Wednesday) to 21 (Friday), 2025.

EdgeTech+ is a platform that adds new value to edge technologies, driven by customer-centric innovation. It is a comprehensive exhibition where visitors can explore the latest technologies essential for driving business transformation.

We invite you to visit and explore our booth at the event.

For more information about EdgeTech+ 2025, please visit [this page].

For details about Yamasaki Laboratory’s booth, please click [here].

We are pleased to announce that an article about our “Nonstop Processor” has been published by The Denpa Shimbun.

The article highlights the unique features of the Nonstop Processor developed by our laboratory, as well as its future prospects.

Link to the article: https://dempa-digital.com/article/694131

Yahoo! News coverage: https://news.yahoo.co.jp/articles/a75f17c8a2d8a08dae99a0ef754c8784202728b8

We exhibited at University Fair 2025- Innovation Japan, held at Tokyo Big Sight on August 21(Thu) – August 22(Fri).

Our exhibit featured the theme: “Non-stop Processor/Processor for Distributed Real-Time Processing.”

For more details about University Fair 2025, please refer to [this page]

Shota Nakabeppu received the Young Researcher Award from the System Architecture (ARC) Workshop.

• Shota Nakabefu, Nobuyuki Yamazaki, “Non-stop Processor Using MTJ-based Non-volatile Devices”, Presented at the ARC Workshop, March 2024

Wada, Muto and Sanuki presented at 252th System Architecture Conference, the 208th System and LSI Design Technology Conference, and the 68th Embedded Systems Joint Research Presentation (ETNET2025).

URL: https://www.ipsj.or.jp/kenkyukai/event/arc252sldm208emb68.html

March 18 (Thu), 09:00-10:20
[CPSY+DC] High Reliability
(2) Kohei Wada and Nobuyuki Yamasaki, “Design of a Lightweight Codec for Error-Free POF”

March 18 (Fri), 10:35-12:35
[CPSY+ARC] Processor Architecture
(17) Keita Muto and Nobuyuki Yamasaki, “Design of a Compute Unit for GPGPU Using RISC-V ISA”
(19) Haruka Sanuki, Nobuyuki Yamasaki, “Design and Implementation of iRMTvisor: A Hypervisor for RMT Processors with IPC Control”

Sato and Yamazawa presented at The Twelfth International Symposium on Computing and Networking (CANDAR2024).

URL: https://is-candar.org/

November 27th (Wed) 13:30-15:10
“A Learning-based Control Scheme for Prioritized SMT Processor”, Kaname Sato and Nobuyuki Yamasaki

November 28th (Thu) 10:45-12:25
“Context Cache for Multicore RISC-V Processor”, Akira Yamazawa, Tsutomu Itou, Kazutoshi Suito and Nobuyuki Yamasaki