Nobuyuki YAMASAKI     Japanese page

Professor, Dr.Eng.

Affiliation

Department of Information and Computer Science
Faculty of Science and Technology
Keio University
3-14-1, Hiyoshi, Kohoku-ku, Yokohama, 223-8522, JAPAN
TEL: +81-45-560-1061, +81-45-566-1765
FAX: +81-45-560-1064
E-Mail yamasaki@ny.ics.keio.ac.jp

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Career

Mar. 1991,		Received the B.S. degree in Physics from Keio University.
Mar. 1993,		Received the M.S. degree in Computer Science from Keio University.
Mar. 1996,		Received the Dr. of Engineering in Computer Science from Keio University.
Apr. 1996,		Researcher with Electrotechnical Laboratory, Agency of Industrial Science and Technology, MITI.
Oct. 1997 - Sep. 2000,		Researcher with PRESTO (Sakigake21), JST.
Oct. 1998,		Research Associate with Faculty of Science and Technology, Keio University.
Oct. 1998 - Mar. 2001,		COE Researcher with Electrotechnical Laboratory.
Apr. 2000,		Assistant Professor with Faculty of Science and Technology, Keio University.
Mar. 2001 - Mar. 2003,		Researcher with SORST, JST.
Apr. 2002 - Now,		Guest Researcher with Digital Human Research Center, AIST.
Apr. 2004 - Mar. 2013,		Associate Professor with Faculty of Science and Technology, Keio University.
Apr. 2013 - Now,		Professor with Faculty of Science and Technology, Keio University.

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Award

Sept. 1998	Young Investigator Excellence Award, Robotics Society of Japan.
June 1999	Best Paper Award, FPGA/PLD Design Conference.
June 2001	Best Presentation Prize, Robotics-Mechatronics Division Annual Prize, The Japan Society of Mechanical Engineers (JSME).
Sept. 2002	Best Paper Award, Robotics Society of Japan.
July 2004	Best Paper Award, System LSI Design Methodology SIG, Information Processing Society of Japan.
Jan. 2006	Presentation Award, International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems.

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Research Themes

Visualisation of Computer Simulation for Physics (1990 - 1991)

Visualisation of Computation results processed by Distran

Automatic system from description of differential equations to visualisation of the computation result

Electronic Architecture for Personal Robots (1991 - 1996)

Einstein I : Personal Robot

ASPIRE : Functionally Distributed Parallel Computer Architecture by using CISC Processors

ASPIRE II : Functionally Distributed Parallel Computer Architecture by using RISC Processors

Human - Robot - Computer Interface : Active Interface (1993 - 1996)

Office Robot Jijo-2 (1996-1998)

Responsive Processor for Parallel/Distributed Real-Time Control (1997 - )

System-on-a-chip integrating the following functions

Real-Time Communication Link : Responsive Link

RISC Processing Core (SPARC)

Computer I/O Peripherals : SDRAM I/Fs, DMAC, PCI, USB, RS-232C, etc.

Control I/O Peripherals : ADC, DAC, PWM Generators, Pulse Counters, etc.

Responsive Link : Hard Real-Time Communication and Soft Real-Time Communication

Split Transmission of Data and Events (Full-duplex Data Link and Full-duplex Event Link)

The packet with higher priority overtakes other packets at each node.

Packet priority can be replaced with new priority at each node. (Acceleration and Deceleration of Packets)

Standardisation in ISO/IEC SC25 WG4

Standardisation in IPSJ TS WG6

Real-Time Operating System : RT-PULSER (1999 - )

Responsive Multi-Threaded (RMT) Processor for Parallel/Distributed Real-Time Processing (2000 - )

System-on-a-chip integrating the following functions

Responsive Multi-Threaded (RMT) Processing Core (8way)

Real-Time Communication Link : Responsive Link II

Computer I/O Peripherals : DDR SDRAM I/F, DMAC, PCI64, USB2, RS-232C, etc.

Control I/O Peripherals : PWM Generators, Pulse Counters, etc.

Bibliography