Murata, Matsui, and Yamada presented at CPSY/IPSJ-EMB/IPSJ-SLDM/DC in Amami, Japan.
Taro Murata, Kensuke Kaneda, Masayoshi Takasu, Keigo Mizotani, Yusuke Hatori, and Nobuyuki Yamasaki, “A Resource Utilization Aware Method to Improve Throughput on RMT Processor,” IEICE Technical Report, Mar 2015.
Tsukasa Matsui, Shuma Matsui, Keigo Mizotani, and Nobuyuki Yamasaki, “Adaptive Error Correcting Code by Priority on RMT Processor,” IEICE Technical Report, Mar 2015.
Kenji Yamada, Yusuke Hatori, Shuma Hagiwara, Keigo Mizotani, Masayoshi Takasu, and Nobuyuki Yamasaki, “Real-Time Static Voltage and Frequency Scaling on RMT Processor using Instructions Per Clock Cycle Control,” IEICE Technical Report, Mar 2015.
