ETNET2024

Nakabeppu, Nojiri and Yamazawa presented at 248th System Architecture Conference, the 205th System and LSI Design Technology Conference, and the 65th Embedded Systems Joint Research Presentation (ETNET2024).

URL: https://www.ipsj.or.jp/kenkyukai/event/arc248sldm205emb65.html

March 21 (Thu), 09:00-10:40
[CPSY+ARC] Optimization and Power Efficiency
(2) Shota Nakabeppu and Nobuyuki Yamasaki, “Non-stop Processor Using MTJ-based Non-volatile Devices”

March 22 (Fri), 09:00-10:40
[CPSY+ARC] Processor Architecture
(17) Yuta Nojiri and Nobuyuki Yamasaki, “
Design of a RISC-V SMT Processor for Real-Time Systems”
(19) Akira Yamazawa, Tsutomu Ito, Kazuhisa Suitou, Nobuyuki Yamasaki, “Design of Context Cache for Multi-core RISC-V Processors”

ETNET 2022

Makino, Nagura and Yashima presented at CPSY/IPSJ-EMB/IPSJ-SLDM/DC.

Masanari Makino and Nobuyuki Yamasaki, “Design of RMTvisor Hypervisor for RMT Processor” IEICE Technical Report, Mar 2022.

Reo Nagura and Nobuyuki Yamasaki, “Imprecise Mixed Criticality Scheduling for SMT Processor” IEICE Technical Report, Mar 2022.

Kosuke Yashima and Nobuyuki Yamasaki, “Efficient Mixed Criticality System using fluid scheduling” IEICE Technical Report, Mar2022.